Integrated devices on a common compound semiconductor III-V wafer

ABSTRACT

A method of fabricating an integrated circuit on a compound semiconductor III-V wafer including at least two different types of active devices by providing a substrate; growing a first epitaxial structure on the substrate; growing a second epitaxial structure on the first epitaxial structure; and processing the epitaxial structures to form different types of active devices, such as HBTs and FETs.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application is related to the U.S. patent application Ser. No.______, entitled “PROCESS FOR MANUFACTURING EPITAXIAL WAFERS FORINTEGRATED DEVICES ON A COMMON COMPOUND SEMICONDUCTOR III-V WAFER” andfiled concurrently with this application.

BACKGROUND

The integration of heterojunction bipolar transistors (HBTs) or bipolarjunction transistors (BJTs) and field effect transistors (FETs) on asingle silicon substrate is known in the art of BiCMOS. The integrationof HBTs and FETs on a single chip has significantly reduced the size andcost of many electronic devices in use today. Silicon-based HBTs/BJTsand FETs, however, are known to have certain performance limitationsthat make them unattractive for some high-frequency analog applications,such as high efficiency cell phone amplifiers and ICs as employed incurrent wireless communication applications.

The fabrication of HBTs on GaAs and other III-V compound semiconductorsubstrates is also known and is attractive for both its performance,reliability and suitability for wireless applications. Integration ofHBTs and FETs would enable higher levels of integration and wouldprovide improvements in overall integrated circuit performance. However,few practical ways of integrating both HBTs and FETs onto a single GaAssubstrate are known in the art.

One previously described method involved the growth of both HBT and FETstructures on a substrate by selective MBE growth. However, thisapproach provided inconsistent results because of epitaxial (epi) growthinterruption and epi re-growth.

Another previously described method provided a combination of HBTs andFETs on a substrate by using the emitter cap layer of an HBT as a FETchannel. However, the method caused an unacceptably high emitterresistance of the HBT and parasitic effects associated with the baselayer that degraded FET performance.

Other efforts have included the growth of an AlGaAs/GaAs HBT on top of aHigh Electron Mobility Transistor (HEMT) in a single growth process.This process merged a FET into the collector of the HBT through a singleepitaxial growth with only limited success because of poor performancecharacteristics.

A number of other attempts have been made to integrate InGaP/GaAs HBTswith MESFET and HEMT structures. In these attempts, an InGaP layer wasused as the channel for the FET devices. However, the channel had lowmobility and saturation velocity with high linear resistance and poorhigh frequency performance.

Accordingly, a need exists for a method of manufacture that integratesHBT and FET devices on a single compound substrate selected from GroupIII-V materials.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a table indicating the epitaxial layer sequence for anHBT-MESFET structure.

FIG. 2 depicts a substrate used for fabricating an integrated III-Vsemiconductor device used in an illustrated embodiment of the invention.

FIG. 3 depicts of substrate of FIG. 2 with a first epitaxial structurefabricated onto an upper surface.

FIG. 4 depicts the substrate of FIG. 3 with second and third epitaxialstructures fabricated onto the upper surface.

FIG. 5 depicts a simplified view of the integrated III-V semiconductordevice in accordance with an illustrated embodiment of the invention.

FIG. 6 depicts a wafer having a number integrated III-V semiconductordevices fabricated thereon in accordance with an illustrated embodimentof the invention.

FIG. 7 is a table indicating the epitaxial layer sequence for anHBT-PHEMT structure.

FIG. 8 is a flow chart of a fabrication process that includes in-situsubstrate cleaning in accordance with an embodiment of the invention.

FIG. 9A is a graph showing the doping depth profile of a PHEMT-typeepitaxial structure for which the in-situ substrate cleaning process wasnot performed.

FIG. 9B is a graph showing the doping depth profile of a PHEMT-typeepitaxial structure for which an in-situ substrate cleaning process wasperformed.

FIG. 10 is a flow chart of a wafer processing cycle that includes achamber pre-conditioning process according to an embodiment of theinvention.

FIG. 11 is a graph comparing the sub-threshold leakage for PHEMT-typedevices fabricated on epitaxial structures with and without the chamberpre-conditioning process.

SUMMARY

The present application relates to integrated devices on a commoncompound III-V semiconductor wafer.

As used herein, an epitaxial wafer includes a sequence of epitaxiallygrown layers on a semiconductor substrate. The various layers typicallyare lattice-matched and are selected for their particular physical andelectrical characteristics. In some cases, the epitaxial wafer also mayinclude one or more metamorphic or other layers.

In one aspect, the invention includes a method providing a substrate,growing a first epitaxial structure on the substrate, growing a secondepitaxial structure on the first epitaxial structure, and growing athird epitaxial structure on top of the second epitaxial structure. Themethod further includes processing the epitaxial structures to formdifferent types of active devices.

In another aspect, the invention includes a method of fabricating anintegrated III-V semiconductor structure that includes at least twodifferent types of active devices. The method includes providing asubstrate and performing an in-situ substrate cleaning process to reducethe presence of contaminants on the substrate. A first epitaxialstructure is grown on the substrate, and a second epitaxial structure isgrown on the first epitaxial structure. The method includes processingthe epitaxial structures to form different types of active devices.

According to a further aspect, a method of fabricating an integratedIII-V compound semiconductor structure including at least two differenttypes of active devices includes providing a first III-V compoundsemiconductor substrate in a reactor. At least two epitaxial structuresfor different types of devices are grown on the first substrate whilethe first substrate is in the reactor, and the first substrate isremoved from the reactor. The method includes coating inner surfaces ofthe reactor to reduce the release of contaminants from those surfacesduring subsequent process steps, and subsequently providing a secondIII-V compound semiconductor substrate in the reactor. At least twoepitaxial structures for different types of devices are grown on thesecond substrate while the second substrate is in the reactor. Theepitaxial structures on the second substrate are processed to formdifferent types of active devices.

In yet another aspect, a semiconductor structure includes a substrate, afirst epitaxial structure disposed on top of the substrate, and a secondepitaxial structure disposed on top of the first epitaxial structure. Aninterface between the substrate and the first epitaxial structure issubstantially free of contaminants. The epitaxial structures formportions of different types of active devices.

Some implementations may include one or more of the following featuresand advantages.

For example, the epitaxial process may enable growth of FET and HBTdevices as combined structures on a single substrate.

The process may enable production (high volume, successive epitaxialgrowth runs) of FET/HBT structures that accommodate the conflictingrequirements of each specific device type and device epitaxialparameters or constraints.

The process may enable incorporation of selective etch stops, either wetor dry, to selectively contact key layers within each device type.

The process may incorporate sacrificial “lift-off” layers that can befully removed to eradicate one or either device type during subsequentdevice processing.

The process may, or may not, be a single continuous epitaxial depositionprocess.

The process may realize sharp, well defined interfaces and exhibitsufficient layer thickness control so that the FET may be implemented asa Pseudomorphic High Electron Mobility Transistor (PHEMT) device usingepitaxially strained layers and/or delta doping techniques.

The process need not require any specific functionally shared layersbetween the HBT and the PHEMT.

The process may be employed for both planar and non-planar substrates toenable subsequent beneficial processing morphology.

In some implementations, the process is sufficient to achieve a highlyresistive buffer for sufficient device isolation (DC and RF) within theenvironment generated by HBT epitaxial deposition. The process mayinclude ex-situ or in-situ substrate preparation, control over theresistivity of buffer layers and buffer layer sequences.

The process may achieve highly doped contact layers for HBT emitters andHBT bases.

The process may be preferentially implemented in a rotating disk reactor(RDR) MOCVD process but also may be used for alternate MOCVD or MBEtechniques.

The process may be used with GaAs, InP and related Group III-Vcompounds.

The process may encompass any specific HBT/BJT implementation (e.g.,InGaP, AlGaAs emitter, GaAs, InGaAs, InGaAsN base).

Other features and advantages will be readily apparent from thefollowing detailed description, the accompanying drawings and theclaims.

DETAILED DESCRIPTION OF ILLUSTRATED EMBODIMENTS

The process for fabricating an integrated III-V semiconductor device isusually divided into two distinct technological stages or processesoften performed by two different entities in the semiconductor industry.The first stage to produce a semiconductor wafer having a sequence ofepitaxial layers with the desired physical and electrical properties.Such a process is described in U.S. patent application Ser. No. ______,entitled “PROCESS FOR MANUFACTURING EPITAXIAL WAFERS FOR INTEGRATEDDEVICES ON A COMMON COMPOUND SEMICONDUCTOR III-V WAFER” filedconcurrently with this application.

The second stage is to process such an epitaxial wafer by lithographictechniques so that the desired device and circuit topology (includinginterconnections between devices are defined, followed by provisioningor deposition of passive components and electrical contacts, dicing thewafer into discrete integrated circuit chips (ICs), and packaging suchICs into an encapsulated package, a lead frame, or other type of packageso that they may be mounted on a printed circuit board.

The present invention is directed to the second such technologicalprocess—the fabrication of two different types of active devicesintegrated on a common compound semiconductor III-V wafer having asuitable epitaxial structure, and the integrated semiconductor devicesso formed by such a process. In particular, the present inventionincorporates the steps of the first process of fabricating asemiconductor wafer having a sequence of epitaxial layers with thedesired physical and electrical properties, followed by processing theepitaxial structures to form (i) different types of active devices; and(ii) integrated circuits formed by such interconnections of such activedevices, optionally including passive components as well; all on thecommon compound semiconductor group III-V wafer.

In a specific example, a heterojunction bipolar transistor (HBT) andfield effect transistor (FET) may be fabricated on the same substrate.In one embodiment, the HBT is fabricated first. Once the HBT has beenfabricated, a passivation layer can be formed or deposited by standardsemiconductor fabrication techniques over the HBT to protect the HBT.Once the passivation layer has been deposited over the HBT, the FET maybe fabricated. In an alternative embodiment (to be described next), theprocess is reversed.

Details of a particular example for an integrated HBT-MESFET structureon a single substrate are provided in the table of FIG. 1. According tothat example, various epitaxial layers are grown sequentially on asemiconductor substrate 10 (FIG. 2). The columns in the table of FIG. 1indicate, respectively, the function of each layer, as well as thenominal thickness in angstroms (Å), the mole fraction and the carrierconcentration (per cm³) for each layer in the particular implementation.In other implementations, those values may vary. In addition, othersubstrates and layers may be provided, and different types of devicesmay be formed in the resulting structure.

The substrate 10 can be based upon any Group III-V material (e.g.,preferably a semi-insulating GaAs substrate). The set of epitaxiallayers can be grown on the substrate using any known technique (e.g.,VPE, MOCVD or MBE).

In one aspect of the invention, a low leakage buffer layer can beprovided as a first step in creating a first epitaxial structure. Thebuffer layer may include, for example, one or more layers of undopedGaAs or AlGaAs layers. The particular buffer layer in the example ofFIG. 1 has two sub-layers: an undoped GaAs layer on an undoped AlGaAslayer. The buffer layer can help initiate crystal growth and can providethe required pinch-off features of the FET. The buffer layer also canhelp trap unwanted and residual, electronically active impurities andprovide electrical isolation for the subsequently formed devices. Thebuffer layer is particularly important for enabling the proper operationof FETs that are integrated on a common substrate with HBTs.

Next, a first epitaxial structure 12 for the FET may be grown (FIG. 3)over the substrate. The FET structure 12 may include, for example, a 50nanometer (nm) thick undoped GaAs spacer layer and a doped GaAs channellayer of about 150 nm thickness. The channel layer may be doped, forexample, with an n-type dopant having a doping concentration of about2.0×10¹⁷ cm⁻³. The first epitaxial structure 12 also may includeadditional layers, such as an InGaP stop-etch layer and a GaAs contactlayer for the FET.

A separation layer or stop-etch layer may be disposed over the FETlayers as part of a second epitaxial structure 14. Alternatively, or inaddition, a contact layer may be disposed over the first epitaxialstructure 12 as part of the second epitaxial structure 14 (FIG. 4). Thecontact layer serves as the subcollector for the HBT device as well as acap layer for the FET.

Although the particular example discussed here includes a layer that iscommon to the both the FET(s) and HBT(s), in other implementations thedifferent types of devices can be formed in different layers such thatthey do not share a layer in common. Forming the different types ofdevices in different layers allows the electrical or othercharacteristics of the devices to be tuned independently and can providegreater flexibility in their design.

Next, in the particular example of FIG. 1, the other HBT layers can begrown over the contact layer as a third epitaxial structure 16. First,lightly doped n-type GaAs collector layers of about 1,000 nm may begrown, followed by a p-type GaAs base layer of about 100 nm. The GaAslayer may be doped, for example, with carbon to a level of about4.0×10¹⁹ cm⁻³. An InGaP emitter layer of about 50 nm doped with siliconto a level of about 3.0×10¹⁷ cm⁻³ can be grown over the base layer.

The FET and HBT devices, including electrical contacts, can befabricated in the foregoing structure using standard photolithographysteps. FIG. 5 depicts a cross-sectional view of an integrated HBT/FETdevice. As shown, the elevated structure 32 a right side depicts a HBT,and the lower structure 34 depicted on the left side depicts a FET.

In the illustrated example of FIG. 5, contacts 18, 20, 22 for thesub-collector, emitter and base of the HBT can be formed usingphotoresist and etch steps.

A passivation layer can be formed or deposited by standard semiconductorfabrication techniques over the HBT device to protect the HBT device. Avertical barrier 30 also may be provided in the substrate through etchisolation or ion implantation techniques to isolate adjacent the FET andHBT-devices. For example, the barrier can be created using a He+ ionimplantation process.

Next, source and drain contacts 24, 26 of the FET are formed on thewafer using, for example, a metal evaporation and lift-off process. Achannel recess etch may be performed to expose the FET layer. A gate 28then can be formed in the exposed FET layer using another appropriatetechnique (e.g., e-beam evaporation).

FIG. 6 depicts a wafer 50 containing a number of fabricated devices.Once diced, the wafer 50 provides a number of chips 52 each of whichcontains, for example, an integrated HBT and FET. Each chip 52 mayinclude multiple HBTs and FETs as well as one or more passive devicesthat, together with the active devices, are interconnected to form anintegrated circuit. The chip 52 can be encapsulated in a package toprovide external electrical connections. The package may be, forexample, a plastic RF module. Other types of packages can be used aswell.

Structures with multiple epitaxially grown structures also can beprocessed to form other types of integrated active devices. For example,a first epitaxial structure can provide the layers for a PHEMT and asecond epitaxial structure can provide the layers for a HBT.

Details of a particular example for an integrated HBT-PHEMT structure ona single substrate are provided in the table of FIG. 7.

A wafer with the foregoing structure can be processed to form the activeHBTs and PHEMTs as well as any passive devices. The wafer then is dicedto form individual chips each of which contains an integrated circuitthat includes an HBT and a PHEMT. The chip can be encapsulated in apackage with leads to provide external electrical connections.

In some implementations, each chip includes multiple devices in thevarious epitaxial structures. For example, each chip may includemultiple PHEMT devices formed in the first epitaxial structure.

Device characteristics and performance can be adversely impacted, forexample, by the presence of surface contaminants at the interfacebetween the substrate 10 and the first epitaxial structure 12. Examplesof contaminants include silicon (e.g., resulting from polishing the GaAssubstrate), telerium (e.g., from previous wafer runs in whichtelerium-doped InGaAs epi-layers are grown), or excessive levels of O₂.In particular, such contaminants can adversely impact the performance ofFETs such as PHEMTs. Also, excessively aggressive etching techniques(e.g., temperatures or flow rates that are too high) can cause masstransport from exposed reactor surface deposits to the substrate. Theconsequence of such mass transport is formation of conductive paths atthe substrate-epi layer interface or increased substrate surfaceroughness or both, resulting in poor device performance (e.g.,sub-threshold leakage) and poor isolation between devices on the samechip.

According to an aspect of the invention, in order to reduce the amountof contaminants that may be present at the substrate-epi interface, anin-situ substrate cleaning process can be performed. The cleaningprocess, an example of which is described in greater detail below, canbe used to process wafers in a MOCVD reactor in which a platter is usedto hold the wafers being processed. The cleaning process also can beused in other wafer processing equipment.

Preferably, the in-situ cleaning process is performed before growingepitaxial layers on the substrate 10 and can facilitate back-to-backwafer processing runs. The cleaning process can help remove the nativecontamination from the substrate while not inducing mass transport fromthe reactor deposits to the substrate. Thus, the cleaning process canresult in a clean substrate-epilayer interface that provides good deviceisolation.

According to a particular implementation illustrated in FIG. 8, a waferis loaded into the reactor (block 100). The cleaning process exposes theGaAs substrate to a halide-based etchant (e.g., HCl, Cl₂, AsCl₃, PCL₂,AsBr₂), in combination with atomic hydrogen. In a particularimplementation, a chlorine-based etchant such as AsCl₃ is used. In thatcase, the substrate can be exposed, for example, to AsCl₃ and AsH₃ at anelevated temperature (e.g., in the range 400-800° C.). The cleaningprocess can include an AsH₃ exposure step (block 102), an AsCl₃ and AsH₃exposure step for etching the substrate (block 104), followed by anAsH₃-only exposure for surface morphology recovery (block 106). In thisexample, the atomic hydrogen is obtained from the decomposed AsH₃. Afterperforming the in-situ substrate cleaning process, the various epitaxiallayers can be grown (block 108).

For particular implementations in which multiple wafers are processed ina high-speed, rotating disk reactor, a temperature of about 700° C. canbe advantageous for the substrate cleaning process. At highertemperatures, telerium may be released from layers in previous waferprocessing runs. Suitable pressures are in the range of 10 Torr toatmospheric pressure, although a range of about 50-80 Torr isparticularly well-suited for some applications. The exposure to theetchant should be long enough to clean the surface without excessivelydamaging the surface morphology. In some cases, an exposure time ofabout fifteen seconds to several minutes at a flow rate of about 100 cc³can be used at appropriate pressure and temperature. The foregoingfactors may vary from reactor to reactor and may vary depending on theconfiguration of the platter that holds the wafers. Thus, in general,the exposure time, flow rate, pressure and temperature for the cleaningprocess can be adjusted depending on the particular geometry,composition and thickness of the wafer to achieve desired deviceperformance.

FIGS. 9A and 9B are graphs showing the doping profile of a PHEMT-typeepitaxial structures. The horizontal axis indicates depth in angstroms,where the origin (“0”) corresponds to the top surface an AlGaAs barrierlayer. The peak doping concentration (which in the illustrated exampleis somewhat greater than 1 E+18 cm⁻³) corresponds to the InGaAs channel.

FIG. 9A shows the doping profile of a PHEMT-type epitaxial structure forwhich an in-situ halide-based substrate cleaning process was notperformed. A peak in the doping profile appears at a depth of about4,000 angstroms, which corresponds to the interface between the GaAsbuffer layer and the GaAs substrate. Such a peak, which indicates thepresence of charge resulting from contaminants at the buffer-substrateinterface, is undesirable and can adversely impact FET device operationand isolation between devices. The in-situ substrate cleaning processcan result in a dopant concentration at the interface of the substrateand the epitaxial structure that is between ten and hundred times lessthan it would be in the absence of the in-situ cleaning process.

FIG. 9B show the doping profile of a PHEMT-type epitaxial structure forwhich an in-situ chlorine-based substrate cleaning process wasperformed. As can be seen, the doping profile beyond a depth of about1,500 angstroms continuously decreases with no additional peaks,indicating a significant reduction in the contaminants present at thebuffer-substrate interface.

According to another aspect of the invention, in implementations usingan MOCVD or other chamber in which semiconductor wafers are processed,it may be desirable to seal exposed surfaces of the reactor betweenwafer processing runs so as to reduce the release of contaminants fromthose surfaces during subsequent growth steps. Examples of reactorsurfaces from which contaminants may be released include, but are notlimited to, the reactor liner, the walls and ceiling of the reactor, thespindle, probes and screens, as well as a platter that holds thesemiconductor wafers. The release of contaminants from such surfaces canbe particularly problematic for FET-layers formed during a waferprocessing run that follows a previous wafer processing run in whichlayers for HBT devices were formed.

As illustrated by FIG. 10, a first wafer processing run is performed(block 110). The wafer processing run may include, among other steps,loading semiconductor substrates (i.e., wafers) into the reactor,growing one or more epitaxial layers on the substrates and removing thesubstrates from the reactor. Before starting the next wafer processingrun, the chamber pre-conditioning process is performed. In theillustrated implementation, the chamber pre-conditioning processincludes placing one or more dummy GaAs (or other compound III-Vsemiconductor) wafers on the platter to cover the pockets in the platter(block 112), heating the platter to an elevated temperature (e.g., about650° C.) (block 114), and epitaxially growing a thin coating of GaAs (orother compound III-V semiconductor) on the inner surfaces of the reactor(block 116). Such a thin coating (i.e., less than about 3 microns (μm))can encapsulate any contaminants, such as telerium, that may be presenton the inner surfaces of the reactor. For some implementations, acoating having a thickness of about 0.25 μm is sufficient. Preferably,the sealing process should be performed as quickly as possible to reducethe overall manufacturing cycle time. In a particular implementation,the process can be completed in less than about five minutes. Aftergrowing the coating, the platter is cooled (block 118), and the dummywafers are removed from the reactor (block 120). A new batch of III-Vsemiconductor substrates then can be processed in the reactor (block122).

It is desirable to cover the pockets of the platter with dummy wafers(e.g., GaAs or silicon) during the chamber pre-conditioning process soas to increase the useful lifetime of the platter. However, the chamberpre-conditioning process can be performed without covering the pockets.

For fabrication processes in which both the in-situ substrate cleaningprocess and the chamber pre-conditioning process are performed, thesubstrate cleaning process can be performed more aggressively, forexample by using higher temperatures (e.g., 700-800° C.). The highertemperatures can allow any in-situ thermal or chemical cleaning processto be performed more quickly without risk that contaminants on theplatter will be transferred to the surface of the substrate. Performingsuch processes more quickly can result in shorter manufacturing cycles.

The foregoing substrate cleaning process and chamber pre-conditioningprocess can be particularly useful when fabricating an integrated III-Vsemiconductor structure with epitaxial structures that include at leasttwo different types of active devices. Reducing the contaminants at thesubstrate-epitaxial layer interface, and possibly at other interfaces aswell, can significantly improve device performance.

FIG. 11 illustrates voltage-versus-current curves for PHEMT-type devicesin an epitaxial structure. The measurements were obtained using amercury probe. The curve 120 corresponds to a device fabricated in anepitaxial structure which was grown without performing the in-situsubstrate cleaning process and the chamber pre-conditioning process. Ascan be seen from the curves, the device exhibited significantsub-threshold current leakage. In contrast, the curve 122 corresponds toa device fabricated in an epitaxial structure which was grown afterperforming the chamber pre-conditioning process and the in-situsubstrate cleaning process. The curve 122 indicates a significantreduction in sub-threshold current leakage.

Other implementations are within the scope of the claims.

1. A method of fabricating an integrated III-V semiconductor structureincluding at least two different types of active devices comprising:providing a substrate; performing an in-situ substrate cleaning processto reduce the presence of contaminants on the substrate; growing a firstepitaxial structure on the substrate; growing a second epitaxialstructure on the first epitaxial structure; and processing the epitaxialstructures to form different types of active devices.
 2. The method ofclaim 1 including processing the epitaxial structures so that the firstepitaxial structure forms at least part of a first type of device andthe second epitaxial structure forms at least part of a second type ofdevice.
 3. The method of claim 2 wherein one of the first and secondtypes of devices is a FET and the other type of device is a HBT.
 4. Themethod of claim 2 wherein one of the first and second types of devicesis a PHEMT and the other type of device is a HBT.
 5. The method of claim1 wherein performing an in-situ substrate cleaning process includesexposing the substrate to a halide-based etchant.
 6. The method of claim1 wherein performing an in-situ substrate cleaning process includesexposing the substrate to a halide-based etchant and hydrogen.
 7. Themethod of claim 6 wherein the in-situ substrate cleaning processincludes: exposing the substrate to a hydrogen-containing gas;subsequently etching the substrate by exposing the substrate to achlorine-based etchant and the hydrogen-containing gas; and subsequentlyexposing the substrate to the hydrogen-containing gas only.
 8. Themethod of claim 6 including performing the cleaning process at atemperature greater than 400° C.
 9. The method of claim 8 includingperforming the cleaning process at a pressure in a range of between 10Torr and atmospheric pressure.
 10. The method of claim 6 includingperforming the cleaning process at a temperature in a range of 600-700°C.
 11. The method of claim 10 including performing the cleaning processat a pressure in a range of 50-80 Torr.
 12. The method of claim 6including exposing the substrate to a halide-based etchant and hydrogenfor a duration of several minutes or less.
 13. The method of claim 1wherein performing the in-situ substrate cleaning process includesexposing the substrate to AsCl₃ and AsH₃
 14. The method of claim 1wherein a dopant concentration at an interface of the substrate and theat least one epitaxial structure is between ten and hundred times lessthan it would be in the absence of the in-situ cleaning process.
 15. Themethod of claim 1 wherein growing at least one epitaxial structureincludes growing a layer to serve as a channel for an active device,wherein a doping profile from the channel layer to a surface of thesubstrate decreases substantially continuously.
 16. The method of claim1 wherein a dopant concentration at an interface of the substrate andthe at least one epitaxial structure is substantially smooth.
 17. Asemiconductor structure comprising: a substrate; a first epitaxialstructure disposed on top of the substrate; and a second epitaxialstructure disposed on top of the first epitaxial structure; wherein theepitaxial structures form portions of different types of active devicesand wherein an interface between the substrate and the first epitaxialstructure is substantially free of contaminants.
 18. The semiconductorstructure of claim 17 wherein a doping profile at an interface of thesubstrate and the first epitaxial structure is substantially smooth. 19.The semiconductor structure of claim 17 wherein the first epitaxialstructure includes a layer to serve as a channel for an active device,wherein a doping profile from the channel layer to a surface of thesubstrate decreases substantially continuously.
 20. An integratedcircuit package comprising: a housing; a semiconductor structure in thehousing, wherein the semiconductor structure includes: a substrate; afirst epitaxial structure disposed on top of the substrate, wherein aninterface between the substrate and the first epitaxial structure issubstantially free of contaminants; a second epitaxial structuredisposed on top of the first epitaxial structure, wherein the first andsecond epitaxial structures form portions of different types of activedevices that are electrically connected; and electrical contacts for theactive devices; and external electrical connections electrically coupledto the contacts.
 21. The integrated circuit package of claim 17 whereinthe semiconductor structure further includes passive deviceselectrically coupled to the active devices.
 22. The integrated circuitpackage of claim 20 wherein the housing comprises an encapsulatedplastic module.
 23. A method of fabricating an integrated III-V compoundsemiconductor structure including at least two different types of activedevices, the method comprising: providing a first III-V compoundsemiconductor substrate in a reactor; growing at least two epitaxialstructures for different types of devices on the first substrate whilethe first substrate is in the reactor; removing the first substrate fromthe reactor; coating inner surfaces of the reactor to reduce the releaseof contaminants from those surfaces during subsequent process steps;subsequently providing a second III-V compound semiconductor substratein the reactor; growing at least two epitaxial structures for differenttypes of devices on the second substrate while the second substrate isin the reactor; and processing the epitaxial structures on the secondsubstrate to form different types of active devices.
 24. The method ofclaim 23 including processing the epitaxial structures on the secondsubstrate so that a first epitaxial structure forms at least part of afirst type of device and a second epitaxial structure forms at leastpart of a second type of device.
 25. The method of claim 24 wherein oneof the first and second types of devices is a FET and the other type ofdevice is a HBT.
 26. The method of claim 24 wherein one of the first andsecond types of devices is a PHEMT and the other type of device is aHBT.
 27. The method of claim 23 wherein the coating comprisessubstantially the same material as the III-V semiconductor substrate.28. The method of claim 27 wherein the coating is grown epitaxially. 29.The method of claim 27 wherein the coating comprises GaAs.
 30. Themethod of claim 27 wherein the coating has a thickness of less thanabout 3 μm.
 31. The method of claim 23 including separating the secondsubstrate into individual integrated circuit chips each of whichincludes at least two different types of active devices.
 32. A method offabricating an integrated III-V semiconductor device comprising:providing a substrate; growing a first epitaxial structure on thesubstrate; growing a second epitaxial structure on the first epitaxialstructure; growing a third epitaxial structure on top of the secondepitaxial structure; and processing the epitaxial structures to formdifferent types of active devices.
 33. The method of claim 32 whereinthe first and second epitaxial structures have a composition andthickness designed for fabrication into a first semiconductor devicewith first operational characteristics.
 34. The method of claim 33wherein the second and third epitaxial structures have a composition andthickness designed for fabrication into a second semiconductor devicewith second operational characteristics.
 35. The method of claim 34wherein growing the second epitaxial structure includes growing acontact layer that is shared by the first and second semiconductordevices.
 36. The method of claim 33 wherein the first semiconductordevice further comprises a herterojunction bipolar transistor.
 37. Themethod of claim 33 wherein the first semiconductor device furthercomprises a field effect transistor.
 38. The method of claim 34 whereinthe second semiconductor device comprises a herterojunction bipolartransistor.
 39. The method of claim 34 wherein the second semiconductordevice comprises a field effect transistor.
 40. The method of claim 32semiconductor device wherein the substrate comprises GaAs.
 41. Themethod of claim 32 wherein growing the first epitaxial structureincludes growing a low leakage buffer layer on the substrate.
 42. Themethod of claim 41 wherein growing the buffer layer includessequentially growing a plurality of epitaxial layers of differentmaterials.
 43. The method of claim 41 wherein growing the buffer layerincludes sequentially growing a plurality of epitaxial layers ofdifferent III-V semiconductor materials.
 44. The method of 41 whereingrowing the buffer layer includes: growing an undoped epitaxial AlGaAslayer on the substrate; and growing an undoped epitaxial GaAs layer onthe AlGaAs layer.
 45. An integrated pair of HBT and FET transistors on acommon compound semiconductor III-V layer.
 46. An integrated pair of HBTand FET transistors sharing a common compound semiconductor III-Vepitaxial layer.